Answered: 8. Assume a cache with a write-through policy, non-write allocate. Your cache has a miss rate of 4%. There is a 120 cycle miss penalty. Additionally, it takes… | bartleby
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3. (7 pts) The program described below runs on a multiple issue processor with a 3-level CPU cache, a 4 GHz clock frequency, and the following performance metrics:Level Miss Penalty R/W Data Miss Rate Instruction Miss RateL1 cache 2 5% 2%L2 cache 5 2% 1.3%Main 100 .3% .1%Instruction Class Instruction Count IPCBranch/Jump 2 × 10^5 1.1Load/Store 4.1 × 10^4 .9Arithmetic 3.6 × 10^6 1.5Float Add 5.5 × 10^5 .25* Note IPC not CPI is provided due to multiple issuea. (2 pts) What is the base CPU time of
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