IEEE

A 40-GS/s 8-bit Time-Interleaved ADC Featuring SFDR-Enhanced Sampling and Power-Efficient Time-Domain Quantization in 28-nm CMOS

Abstract: This article reports a 40-GS/s 8-bit time-interleaved (TI) time-domain (TD) gated-ring-oscillator analog-to-digital converter (GRO-ADC). An interleaving number of 32 is achieved with a ...
IEEE

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment

Abstract: This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub-$\mu $ s locking time when synthesizing millimeter-wave (mm-wave) ...