IEEE

Programmable Delay-Line with High-Resolution Time Steps Implemented in a Digital-to-Time Converter IP-Core for FPGAs and SoCs

Abstract: In this paper, we present an innovative Digital-to-Time Converter Programmable Delay Line (DTC-PDL) IP-Core to generate a delay with a high resolution for Xilinx Field-Programmable Gate ...
IEEE

Programmable True Time Delay Lines Using Integrated Waveguide Meshes

Abstract: We analyze and explore the potential that waveguide-mesh-based architectures used in programmable photonic integrated circuits can be configured to enable true time optical delay lines, ...
GitHub

d3-timer

This module provides an efficient queue capable of managing thousands of concurrent animations, while guaranteeing consistent, synchronized timing with concurrent or staged animations.