IEEE

Programmable Analog-to-Digital Converter Array Supporting Architecture Restructuring and Mode Concurrency

Abstract: This work presents a new analog-to-digital converter (ADC) architecture named programmable converter array (PCA) for multi-standard signal acquisition. Unlike prior reconfigurable ADCs that ...
IEEE

Design and Field-Programmable Gate Array Realization of a Multirate Multisampling Algorithm for Improving Signal-to-Noise Ratio in Pulse Compression Radars

Abstract: Due to the ongoing advancements in small unmanned systems (SUSs), the field of study on detecting targets with small radar cross section (RCS) areas is constantly expanding. Due to their ...
Design-Reuse

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
GitHub

dortizbarrientos/tutorials-Quant-Gen

Welcome. This repository contains a Quarto book that connects biological mechanism to the matrix algebra used in modern quantitative genetics. Most resources jump straight to (y = Xb + Zu + e). This ...