Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
A novel AI-acceleration paper presents a method to optimize sparse matrix multiplication for machine learning models, particularly focusing on structured sparsity. Structured sparsity involves a ...
ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...
RISC-V chip designer SiFive is introducing two new processors that the company says are designed for high-performance, energy-efficient applications such as wearables, smart home devices, virtual ...
For those not immediately familiar with RISC-V, it is a relatively new CPU architecture which takes advantage of Reduced Instruction Set Computer (RISC) principles. RISC-V is an open standard ...
Imperas has extended its Risc-V reference model and simulator to cover forthcoming vector instructions and to support coverage-driven verification analysis. Called riscvOVPsim, the enhanced version ...
ARM has unveiled a new, highly flexible type of vector processing instruction that it plans to debut in HPC markets and businesses. Share on Facebook (opens in a new window) Share on X (opens in a new ...
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