EDN

Breker Verification Systems Unleashes the SystemUVM Initiative to Empower UVM Engineering

Breker Verification Systems used the opening of DVCon U.S. today to unveil SystemUVM, a framework designed to simplify specification model composition for test content synthesis with a ...
Semiconductor Engineering

Continuing Challenges For Open-Source Verification

Experts at the Table: This is the last part of the series of articles derived from the DVCon panel that discussed Verification in the Era of Open Source. It takes the discussion beyond what happened ...
Semiconductor Engineering

Verification Tools Straining To Keep Up

Verification engineers are the unsung heroes of the semiconductor industry, but they are at a breaking point and desperately in need of modern tools and flows to deal with the rapidly increasing ...
Business Insider

Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release

ELK GROVE, Calif., Feb. 04, 2025 (GLOBE NEWSWIRE) -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design ...
EDN

Makefile vs. YAML: Modernizing verification simulation flows

Automation has become the backbone of modern SystemVerilog/UVM verification environments. As designs scale from block-level modules to full system-on-chips (SoCs), engineers rely heavily on scripts to ...
Semiconductor Engineering

A Novel Approach For Hardware-Software Co-Verification

The complexity of system on chips (SoCs) continues to grow rapidly. Accordingly, new standards and methodologies are introduced to overcome these verification challenges. The Portable Test and ...
Semiconductor Engineering

ML And UVM Share Same Flaws

A number of people must be scratching their heads over what UVM and machine learning (ML) have in common, such that they can be described as having the same flaws. In both cases, it is a flaw of ...