EDN

PCI Express x1 PHY supports source synchronous and DDR clocking

Dallas, Tex.— Texas Instruments Inc.'s PCI Express (PCIe) x1 physical layer (PHY) chip has hit the market in volume, providing a low-cost PCI Express endpoint device for a wide variety of sectors such ...
Electronic Design

Troubleshoot High-Speed Buses By Clearing "Clock Scheme Fog"

Understand how double-pumped, quad-pumped, and source-synchronous devices work, and you can capture the right data at the right time. High-speed digital buses continuously evolve. Not only are they ...
Electronic Design

Optimize Timing Margins For Your High-Speed Interface

High-speed digital buses have evolved dramatically over the past decade. Not only are they faster, but they're also changing how systems clock data. To improve data throughput, emerging synchronous ...
Design-Reuse

Altera FPGA Enables Industry's Highest Source-Synchronous Data Transfer Rate

Stratix GX Device with Embedded DPA Circuitry Is Industry's Only FPGA Supporting 1-Gbps SPI-4.2 Signaling San Jose, Calif., May 20, 2003— Altera Corporation (NASDAQ: ALTR) today announced that its ...