EDN

How physically aware interconnect IP bolsters SoC design

The network-on-chip (NoC) technology, which connects IP blocks in highly complex system-on-chip (SoC) designs, has ascended to the next logical level by becoming physically aware. According to Andy ...
Electronic Design

Predictive SoC Floorplanning Using Artificial Intelligence

Pain points of the existing floorplan designing process. How artificial intelligence can optimize this process to reduce the time taken from weeks to just hours. Potential applications of expanding ...
Semiconductor Engineering

Simplify DFT For Advanced SoCs

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT ...
Electronic Design

Manage ASIC, SoC Design Risk with Leading-Edge Verification Services

Value in design prototyping using FPGAs. Validating the design with firmware. How the process works. Identifying companies with the right experience and expertise in FPGA and design prototyping ...
EDN

From system design to SiP: What’s the design flow

Like any successful system-on-chip (SoC) effort, a multi-die system-in-package (SiP) project must start with a sound system design. But then what? Are the steps in the SiP design flow different from ...