A new timing-aware fault model was developed using the standard delay file (SDF) information to enable ATPG to create patterns that propagate faults through long paths.2 Such a test has a ...
ATPG targets faults at IC-gate boundaries, but 50% of defects are located within cells. Learn how cell-aware ATPG and user-defined fault models help to ferret out these hard-to-squash bugs.
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