Design And Reuse

RISC-V IP Core Portfolio at Embedded World 2026, Powering Next-Gen Embedded Systems for Automotive, IoT & Industrial Systems…

T2M will be participating in Embedded World 2026, from March 10 to 12, 2026, in Nuremberg, Germany, to showcase its full range of production-proven RISC-V CPU IP cores. Extracted from silicon and ...
Business Wire

OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing

SANTA CLARA, Calif.--(BUSINESS WIRE)--Today, at the RISC-V Summit, the OpenHW Group announced the multi-member CORE-V CVA6 Platform project. The platform is an open-source FPGA-based software ...
Business Wire

Smaller Code, Higher Performance: Latest IAR Embedded Workbench for RISC-V Leverages CoDense™ from Andes

UPPSALA, Sweden--(BUSINESS WIRE)--IAR Systems®, the world leader in software and services for embedded development, has just announced the full support of their latest release of IAR Embedded ...
Design And Reuse

RISC-V IP Core: T2M to Present Production-Proven RISC-V IP Core at Mobile World Congress, 2026

The portfolio comprises both 32/64-bit RISC-V CPUs, offering ISA extensibility, optional accelerators, and customisation at the architecture, microarchitecture, and interface levels. Supporting ISO ...
EDN

Development environment builds RISC-V code

The Efinity RISC-V Embedded Software IDE from Efinix is an Eclipse-based integrated development environment (IDE) powered by Ashling’s RiscFree IDE. Efinity IDE offers intuitive development and ...
Forbes

The RISE Of RISC-V: Accelerating Adoption Through Collaboration And Coordination

In an attempt to accelerate RISC-V adoption, a global consortium of industry leaders has banded together to form the RISC-V Software Ecosystem (RISE) Project. According to the project’s press release, ...
Semiconductor Engineering

RISC-V Is Thriving: Here’s What You Need to Know

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set ...
Hackaday

RISC-V In… Typescript?

We are accustomed to seeing RISC-V implementations in Verilog or VHDL, but [Low Level JavaScript] has one in TypeScript. Before you dismiss it as a mere emulator, know that the project relies on ...
ZDNet

Rediscovering RISC-V: Apple M1 sparks renewed interest in non-x86 architectures

RISC-V is, like x86 and ARM, an instruction set architecture (ISA). Unlike x86 and ARM, it is a free and open standard that anyone can use without getting locked into someone else's processor designs ...
Ars Technica

Google wants RISC-V to be a “tier-1” Android architecture

Over the holiday break, the footage from the recent “RISC-V Summit” was posted for the world to see, and would you believe that Google showed up to profess its love for the up-and-coming CPU ...
InfoWorld

Java port eyed for RISC-V hardware

Port of the JVM to the open-source licensed instruction set architecture could be ready later this year, if project gets approval to proceed. The RISC-V hardware instruction set would get a ...