EDN

Verifying large models in RTL simulation

Verifying that a multi-million gate ASIC will function according to its specification prior to being built into a system composed of hundreds or thousands of additional ASICs plus thousands of other ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Semiconductor Engineering

Distributing RTL Simulation Across Thousands Of Cores On 4 IPU Sockets (EPFL)

“Hardware development relies on simulations, particularly cycle-accurate RTL (Register Transfer Level) simulations, which consume significant time. As single-processor performance grows only slowly, ...
Semiconductor Engineering

Hardware-Accelerated RTL Simulator

A technical paper titled “Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism” was published by researchers at EPFL, University of Tokyo, Sharif University, and ...
EDN

Modeler connects RTL, SystemC simulation

SAN JOSE, Calif. — Adding a proverbial tiara to its Miss Univers line of hardware/software co-verification tools, Adveda Inc. is introducing this week a model generator simulation add-on that places a ...