If you are one of the more than 2 billion smartphone users today, it is hard to imagine life without one! Breaking new frontiers, wearable smart devices and the Internet of things are the latest buzz.

Much of what's emerged from the Cadence/Verisity merger has been aimed toward addressing the lack of predictability in the verification process. Cadence has spent a good deal of time and energy ...

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...

Many of today's large, complex designs can contain thousands of lines of Verilog or VHDL code. Quite often, teams of engineers—with some members possibly situated in disparate locations worldwide—will ...

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...

The cost of SOC (system-on-chip) design continuesto skyrocket, market windows continueto shrink, and design complexity continues togrow exponentially. These challenges are onlya few of those that SOC ...

Electronic Design Automation is largely about saving time in the development of electronic designs. EDA tools strive to reduce verification time, design cycle time, and time to market. EDA is ...