EDN

Low power implementation techniques for ASIC physical design

In the semiconductor domain, the operating frequency of devices and the number of transistors in a single module increase over time. In this article, we will look at widely known low power ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Electronic Design

Low-Power Design With Multi-VDD Flows

Nearly all designs at advanced process nodes need some sort of power-saving strategy. As more designs employ advanced low-power techniques, design teams are discovering huge implementation hurdles ...
Electronic Design

Low Current, Power Measurements Require Extreme Accuracy

Key considerations for using a low current source include the maxi­mum current, minimum current, and step resolution; the output settling time required; and the level of voltage compliance needed. It ...