EDN

Incorporating AI into Low-Power Chip Design

The aim of low-power design is to reduce the overall dynamic and static power consumption of an integrated circuit (IC), a crucial aspect for enabling next-generation applications. This procedure ...
TechRepublic

Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown ...
Semiconductor Engineering

Low-Power IC Design Without Compromise

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA ...
Semiconductor Engineering

Lower Power Chips: What To Watch Out For

Low-power design in advanced nodes and advanced packaging is becoming a multi-faceted, multi-disciplinary challenge, where a long list of issues need to be solved both individually and in the context ...
Electronic Design

Ultra-Low Power Timers Cut Effects of Leakage Currents

A family of ultra-low-power system timers is intended specifically for reducing power during system sleep time. These ICs, called nanotimers, provide various methods for a system to enter a no-power ...
EDN

Low Power System Design Techniques Using FPGAs

The advantage of utilizing a combination of low-power components in conjunction with low-power design techniques is more valuable now than ever before. Requirements for lower power consumption ...