EDN

Engineer creates open-source HDL in Ruby language

PORTLAND, Ore. — Illustrating the power of the Ruby scripting language, consulting engineer Phil Tomson has used it to create the open-source Ruby hardware-description language (RHDL). Not currently ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
EDN

Engineer creates HDL generation language

SANTA CRUZ, Calif. — A declarative, functional programming language that eases RTL code generation is now going into beta sites, and is available for free downloading from the creator's web site. The ...
Design-Reuse

Lattice and Aldec Announce New Alliance For FPGA Design And Verification

Simulator Delivers Industry Leading Speed, and is the Only OEM Mixed Language Simulator for FPGA Design HILLSBORO, OR - April 21, 2008 - Lattice Semiconductor Corporation (NASDAQ: LSCC) and Aldec, ...
Electronic Design

EDA Update: Mixed HDL/C-Language Design For FPGAs

Mixed HDL/C-Language design for FPGAs recently debuted, courtesy of Aldec Inc. and Celoxica Ltd. The Active-HDL+C integrated FPGA design environment combines Aldec's Active-HDL design entry and ...