EDN

Designers stand up for gate-level simulation

SANTA CRUZ, Calif. — In theory, static timing analysis and formal verification should render gate-level simulation unnecessary. But in reality, it's unavoidable, according to a number of engineers who ...
Semiconductor Engineering

Writing Reusable UPF For RTL And Gate-Level Low Power Verification

The Unified Power Format (UPF) is used to specify the power intent of a design. Once written, the UPF file is applied at every stage of the design cycle — starting with the RTL, then the gate-level, ...
Electronic Design

Instant "Replay" Comes To Timing Simulation

Novas Software's Siloti Replay technology streamlines the process of detecting, isolating, and fixing the source of timing problems using gate-level simulation. The module yields significantly faster ...
Design-Reuse

Avery Design Systems Unveils SimXACT for Elimination of X Pessimism Issues in Gate-Level Simulation and Upgrades XVER X Verification

ANDOVER, Mass.-- March 23, 2012--Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of its revolutionary X verification solution, ...
EDN

DDR interface gate-level simulation advantages

No matter how advanced Static Timing Analysis (STA) tools become, there are still a lot of advantages to running GLS, since it has the capability of uncovering a lot of hidden design issues which are ...
Design-Reuse

Accurate System Level Power Estimation through Fast Gate-Level Power Characterization

Low power consumption is becoming a critical factor for System-on-a-Chip (SoC) designs. System level power estimation for SoCs has gained importance with the increase of SoC design complexity. This ...