EDN

A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your ...
EDN

How to build reliable FPGA memory interface controllers without writing your own RTL code!

As FPGA designers strive to achieve higher performance while meeting critical timing margins, one consistently vexing performance bottleneck is the memory interface. Today's more advanced FPGAs ...
Hackaday

JTAG Dongle Pushes Code To FPGA After Bootup

This gnarly beast has near-magical qualities. [Sprite_TM] patched it together as a dongle which attaches to a JTAG header (we’re fairly certain this is not a standard footprint for that interface ...
Electronic Design

FPGA Design Flow Takes Simulink Code Into Synthesis

Thanks to collaboration between The MathWorks and Mentor Graphics, MathWorks’ Simulink HDL Coder users gain a smooth path into synthesis. Mentor’s Precision Synthesis tool now supports HDL generated ...
Semiconductor Engineering

Challenges In Using HLS For FPGA Design

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved ...
Electronic Design

Programming FPGA Systems: Code Conversion

Code Conversion On the left side below is the ANSI-C software code that makes the call to the C Hough function. The input to the Hough function is the image to be processed (TileIn). The output of the ...
Hackaday

FPGA-and-Pi Colossus Smashes Your Codes!

If it were sixty years ago, and you were trying to keep a secret, you’d be justifiably glad that [Ben North] hadn’t traveled back in time with his Raspberry-Pi-and-FPGA code-breaking machine. We’ve ...
Design-Reuse

"Lattice Diamond" FPGA Design Software Heralds New Era for Low Power, Cost Sensitive FPGA Applications

HILLSBORO, OR, Jun 28, 2010 -- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 1.0 of its Lattice Diamond(TM) FPGA design software, the new flagship design environment for ...
Geeky Gadgets

Intel Cyclone 10 FPGA and STM32H7 MCU combined to create USB2IO high-speed interface explorer

MCU – STMicro STM32H743 Arm Cortex-M7 @ 480MHz CPU clock An external 64MB QSPI flash for extra FPGA code storage; FPGA – Intel Cyclone 10LP (10CL040) with 40k logic elements, 1,134 Mbit embedded ...
Design-Reuse

A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your ...