EDN

Inferring Stratix V DSP Blocks

Different features of the Stratix V variable precision DSP blocks are useful for efficient configuration of different FIR filter variations. The DSP blocks can be programmed in different operational ...
EDN

Hardened Floating-Point DSP Blocks

Altera Corporation changed the game as it relates to floating-point DSP performance in an FPGA. Altera is the first programmable logic company to integrate hardened IEEE 754-compliant, floating-point ...
New Electronics

Altera builds hardened DSP blocks into Arria and Stratix at 20nm

Responding to the increasingly demanding task of designing floating point DSP capability into FPGAs, Altera has integrated IEEE754 compliant, floating point operators into Arria 10 and Stratix 10 ...
Electronic Design

An Easier Path To RTL For DSP Algorithms

Why are so many designers turning to FPGA implementation for DSP designs? Considering the price/performance ratio for today's high-end FPGAs, not to mention the large numbers of DSP blocks and ...
Design-Reuse

Xilinx Ships World's Highest Performance DSP Platform with New Virtex-5 SXT FPGAs

Integrated platform combines enhanced DSP blocks for parallel processing, highest memory-to-logic ratio, and low-power serial transceivers for highest I/O bandwidth SAN JOSE, Calif., February 5, 2007 ...
Design-Reuse

Altera's "Code:DSP" Initiative Accelerates FPGAs Into DSP Mainstream

San Jose, Calif., September 3, 2002 — Altera Corporation (NASDAQ: ALTR) today launched Code:DSP, a major initiative to extend the reach of FPGAs from multi-channel, high-performance signal ...
Electronic Design

Use 1TRAM Blocks To Embed More Memory On Logic Chips

Data refresh and cell-layout issues must be addressed to optimally implement this space-saving alternative to SRAM technology. As the system-on-a-chip (SoC) era marches forward, there's a pressing ...