EDN

Synopsys updates DFT tool suite; ATPG offering gets delay option

BALTIMORE — Claiming a huge boost in capacity and speed, Synopsys Inc. is announcing a hierarchical capability for its Design For Test (DFT) Compiler product at this week's International Test ...
EDN

Complex SoC Testing with a Core-Based DFT Strategy

With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically &#8212 making it almost impossible to test an entire design once it ...
Electronic Design

DTF And ATPG Enhancements, Improve Compiler Performance

A series of design-for-test (DFT) and automatic pattern generation (ATPG) products leverage advanced test modeling for dramatic capacity and performance gains in Synopsys' DFT Compiler. The TetraMAX ...
Design-Reuse

Synopsys adds timing-defect option to test generator, boosts design-for-test compiler

BALTIMORE--At the International Test Conference here today, Synopsys Inc. announced new advanced test modeling technology that will more than triple the capacity of the company's design-for-test ...
Electronic Design

DFT app supports hardware emulation

Design for testability (DFT), a way to build testability into an integrated circuit (IC) at the design stage to lower testing costs and increase manufacturing yield, has been around for many years in ...