SOCAMM2 Is The Memory Standard AI Is Looking For

AI infrastructure can't evolve as fast as model innovation. Memory architecture is one of the few levers capable of ...
Semiconductor Engineering

A Primer On Last-Level Cache Memory For SoC Designs

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
Forbes

Memory And Design Advances From The AI Infra Summit

Forbes contributors publish independent expert analyses and insights. This article discusses memory and chip and system design talks at the 2025 AI Infra Summit in Santa Clara, CA by Kove, Pliops and ...
EDN

Cache and Memory Hierarchy Design

• Designed a generic Cache simulator module and modeled L1, L2 caches augmented with a Victim Cache. • Implemented using C++ and evaluated with SPEC address traces for gcc, perl, vortex, compress and ...
Electronic Design

Hardware Compression Works at the Memory Cache Level

How lossless data compression can reduce memory and power requirements. How ZeroPoint’s compression technology differs from the competition. One can never have enough memory, and one way to get more ...
The Next Platform

Cache Is King

The gap between the performance of processors, broadly defined, and the performance of DRAM main memory, also broadly defined, has been an issue for at least three decades when the gap really started ...
Electronic Design

Server Processors Stack Up to 1.1 GB of 3D Cache

AMD is leveraging one of its latest families of EPYC server CPUs, code-named Genoa X, in-house to run the electronic design automation (EDA) tools it uses for product development. Based on TSMC's 5-nm ...