Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...
Design-Reuse

Using OCP and Coherence Extensions to Support System-Level Cache Coherence

Open Core Protocol (OCP) [1][2] is a common standard for Intellectual Property (IP)core interfaces. OCP facilitates IP core plug-and-play and simplifies reuse by decoupling the cores from the on-chip ...
Semiconductor Engineering

The High But Often Unnecessary Cost Of Coherence

Cache coherency, a common technique for improving performance in chips, is becoming less useful as general-purpose processors are supplemented with, and sometimes supplanted by, highly specialized ...
Design-Reuse

Adding Cache to IPs and SoCs

• Cache memory significantly reduces time and power consumption for memory access in systems-on-chip. • Technologies like AMBA protocols facilitate cache coherence and efficient data management ...