Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought ...

This article is about our experience in applying formal verification techniques to an ASIC design in a large communication system. When we, in the Alcatel-Lucent IC design group in Nürnberg, Germany, ...

Formal verification shortens the time it takes to verify a design by finding bugs earlier in the product-development cycle (Figure 1). Formal-verification tools' ability to improve design debugging ...

A crucial step in design flow is to ensure that the gate-level design representation of an ASIC or system-on-a-chip (SoC) matches the RTL description through formal equivalence checking.... A crucial ...

Targeted for users of next-generation physical design closure tools, customer-owned tooling (COT) flows, and advanced ASIC flows, a new suite of formal verification products reaches into the physical ...